FEC frame structuring method and FEC multiplexer
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United States of America Patent
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-
Mar 15, 2005
Grant Date -
Sep 12, 2002
app pub date -
Oct 9, 2001
filing date -
Dec 7, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is returned to the original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct errors in the information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit 37.
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