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Abstract

A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line. The semiconductor integrated circuit comprises a first clock-signal generating circuit which generates a clock signal of N phases synchronized with an input clock signal, a second clock-signal generating circuit which generates a clock signal of M phases synchronized with one phase selected from among the N-phase clock signal generated by the first clock-signal generating circuit, and in which N.noteq.M holds, and a computation circuit which finds a control value for use in selecting one phase from among the N-phase clock signal, on the basis of the logic value of the serial transmission data sampled using the N-phase clock signal and the M-phase clock signal.

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First Claim