Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 1, 2005
Grant Date -
Apr 1, 2004
app pub date -
Sep 17, 2003
filing date -
Jun 15, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully