Method for manufacturing merged DRAM with logic device
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United States of America Patent
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-
Feb 22, 2005
Grant Date -
Jul 1, 2004
app pub date -
Jun 30, 2003
filing date -
Dec 26, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In manufacturing merged DRAM with a logic device in a single chip, an oxide layer and a nitride layer are formed on a semiconductor substrate. A hole for exposing the substrate is formed. A silicon epitaxial layer is grown on a portion of the substrate exposed by the hole and an adjacent portion of the nitride layer so that a facet is formed on the nitride layer surface. A thermal oxide layer is grown on the silicon epitaxial layer. The thermal oxide layer is wet etched so that only a growing portion is left on the silicon epitaxial layer. The thermal oxide layer left on the facets of the repeatedly grown silicon epitaxial layer is removed. A gate oxide layer and a gate conductive layer are formed on the resulting substrate. A gate is formed by patterning the gate conductive and oxide layer. A capacitor having a storage node, a dielectric layer, and a plate node is also formed.
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