Semiconductor substrate with trenches for reducing substrate resistance

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6858471
SERIAL NO

10247906

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Abstract

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In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.

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Patent Owner(s)

Patent OwnerAddress
VISHAY-SILICONIX2201 LAURELWOOD ROAD SANTA CLARA CA 95054

International Classification(s)

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  • 2002 Application Filing Year
  • H01L Class
  • 14069 Applications Filed
  • 7752 Patents Issued To-Date
  • 55.10 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances200220032004200520062007200820092010201120122013201420150255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kasem, Mohammed Santa Clara, CA 12 124
Korec, Jacek San Jose, CA 63 2629
Xu, Robert Q Fremont, CA 9 179

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Patent Citation Ranking

  • 6 Citation Count
  • H01L Class
  • 2.00 % this patent is cited more than
  • 20 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges56113063435821410785533224218401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05010015020025030035040045050055060065070075080085090095010001050110011501200

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