Ultra-high linearity RF passive mixer
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United States of America Patent
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Jan 25, 2005
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app pub date -
Feb 28, 2002
filing date -
Feb 28, 2002
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Abstract
A CMOS implemented passive mixer circuit for improving linearity performance in wireless communication systems is described, including dual pairs of NMOS FETs and dual pairs of PMOS FETs. Each NMOS FET is connected in parallel with a corresponding PMOS FET. A local oscillator signal is provided to the gate of one FET while a 180-degree phase shifted local oscillator signal is provided to the gate of its complementary FET. Because the complementary FETs are driven by local oscillator signals that are 180 degrees out of phase, the NMOS FET is turned on for at least a portion of the positive cycle of the local oscillator signal and the PMOS FET is turned on for at least a portion of the negative cycle of the 180-degree phase shifted local oscillator signal. Distortion in the mixed output signal is thereby reduced.
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