Wafer-level package for micro-electro-mechanical systems
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United States of America Patent
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Jan 25, 2005
Grant Date -
Apr 22, 2004
app pub date -
Jan 27, 2003
filing date -
Oct 17, 2002
priority date (Note) -
Expired
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Abstract
A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.
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