Wafer-level package for micro-electro-mechanical systems

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6846725
APP PUB NO 20040077154A1
SERIAL NO

10351534

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Abstract

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A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICS11 SCIENCE PARK ROAD SCIENCE PARK II 11768

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yu Singapore, SG 837 9647
Kripesh, Vaidyanathan Singapore, SG 20 542
Nagarajan, Ranganathan Singapore, SG 25 853
Premachandran, Chirayarikathuveedu Sankarapillai Singapore, SG 3 157

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