Method of processing a repeat block efficiently in a processor wherein the repeat count is not decremented in a specific case to prevent error in execution
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United States of America Patent
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Jan 18, 2005
Grant Date -
Jul 5, 2001
app pub date -
Dec 29, 2000
filing date -
Dec 30, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention presents a method for processing data in a processor having a processor core for processing a command in a pipeline form. The method comprises the steps of setting a repeat count value; executing a repeat block command to set a repeat ending address and a repeat starting address; comparing the repeat ending address and a memory address of the second command to identify whether they are identical to each other; checking whether the first command is a command for nonlinearly changing an executing order of a program if the repeat ending address and the memory address of the second command are identical to each other; and storing the memory address of the second command while not reducing the repeat count value if the first command is a command for nonlinearly changing the executing order of the program.
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