System and method for the use of reset logic in high availability systems
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United States of America Patent
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Jan 4, 2005
Grant Date -
Dec 19, 2002
app pub date -
May 31, 2001
filing date -
May 31, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of providing reset logic in high availability computer systems is disclosed. The illustrative embodiment of the present invention uses probability theory in combination with redundant processors and components to ensure system availability. Detected errors are verified, and malfunctioning processors or components are then changed to a reset state that functionally removes them from the system. Detected errors which can not be verified result in the processor or component that incorrectly detected the error being placed in a reset state. The use of redundant components and processors enable standby processors to be activated to take the place of reset processors quickly enough to maintain system availability.
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