Substrate with stacked vias and fine circuits thereon, and method for fabricating the same
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United States of America Patent
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-
Jan 4, 2005
Grant Date -
Jul 1, 2004
app pub date -
Aug 29, 2003
filing date -
Dec 31, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.
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