Combined cyclic redundancy check (CRC) and Reed-Solomon (RS) error checking unit
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United States of America Patent
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Dec 28, 2004
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N/A
app pub date -
Feb 1, 2002
filing date -
Feb 2, 2001
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Abstract
An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.
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