Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
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United States of America Patent
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Dec 14, 2004
Issued Date -
N/A
app pub date -
Sep 20, 2002
filing date -
Sep 21, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or 'FETs') that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
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Patent Citation Ranking
- 280 Citation Count
- H01L Class
- 97.63 % this patent is cited more than
- 21 Age
