Semiconductor storage device and test system
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United States of America Patent
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Nov 23, 2004
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N/A
app pub date -
Apr 25, 2001
filing date -
Nov 5, 1998
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Abstract
A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.
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