Memory device
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United States of America Patent
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Nov 9, 2004
Grant Date -
Jun 5, 2003
app pub date -
Dec 3, 2002
filing date -
Dec 4, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance elements. Thus, the area of the memory cell is reduced and no reference voltage is required.
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