Memory system allowing fast operation of processor while using flash memory incapable of random access
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United States of America Patent
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Oct 26, 2004
Grant Date -
Apr 1, 2004
app pub date -
Feb 25, 2003
filing date -
Sep 26, 2002
priority date (Note) -
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Abstract
A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs the parallel data to the main memory. This eliminates the need for the CPU downloading file data from the flash memory to the main memory, allowing connection of a non-volatile memory with a large capacity, without reduction in the processing speed of the system.
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