High speed digital counters
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United States of America Patent
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Sep 21, 2004
Grant Date -
Sep 11, 2003
app pub date -
Jan 31, 2003
filing date -
Jan 31, 2002
priority date (Note) -
Expired
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Abstract
A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
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