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United States of America Patent
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Sep 14, 2004
Grant Date -
Nov 22, 2001
app pub date -
Feb 28, 2001
filing date -
Apr 26, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
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