Synchronization of vertical retrace for multiple participating graphics computers
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United States of America Patent
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Sep 14, 2004
Grant Date -
Aug 29, 2002
app pub date -
Nov 27, 2001
filing date -
Nov 27, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
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