Analog hold cell in a CMOS process
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United States of America Patent
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Sep 14, 2004
Grant Date -
N/A
app pub date -
Jul 2, 2002
filing date -
Jul 2, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.
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