System and method for low area self-timing in memory devices
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United States of America Patent
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Sep 7, 2004
Grant Date -
Aug 12, 2004
app pub date -
Feb 10, 2003
filing date -
Feb 10, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An invention for self-timing in a memory device is provided. The self-timing system includes a dummy global wordline signal, which is configured to follow a global timing pulse for a memory device. In addition, a row of at least one non-timing memory banks is included. Each non-timing memory bank includes a model row in electrical communication with the dummy global wordline signal. Each model row is comprised of a plurality of load cells. The self-timing system further includes a timing memory bank having a global timing column. The global timing column is comprised of a plurality of load cells that are coupled via at least one bitline. In operation, the global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks.
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