Systems and methods for use in reduced instruction set computer processors for retrying execution of instructions resulting in errors
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United States of America Patent
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Aug 31, 2004
Issued Date -
N/A
app pub date -
Mar 13, 2001
filing date -
Jun 5, 1998
priority date (Note) -
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Abstract
Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.
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