Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
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United States of America Patent
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Aug 31, 2004
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N/A
app pub date -
Mar 19, 2002
filing date -
Mar 19, 2002
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Abstract
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.
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