Combinational test pattern generation method and apparatus

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United States of America Patent

PATENT NO 6782502
SERIAL NO

10262271

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Abstract

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A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS AMERICA INC1001 MURPHY RANCH ROAD MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Koe, Wern-Yan San Jose, CA 9 110

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