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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
SGS-THOMSON MICROELECTRONICS S A	GINTILLY

International Classification(s)

• H02H:EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Claverie, Isabelle	Marseille, FR	3	9
# of filed Patents : 3 Total Citations : 9

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Patent Citation Ranking

• 3 Citation Count
• H02H Class

• 4.49 % this patent is cited more than
• 21 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

Full Text

US Patent No: 6781804

Protection of the logic well of a component including an integrated MOS power transistor

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Abstract

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The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

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Description

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Claims

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