RISC processor with a debug interface unit
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United States of America Patent
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Jul 20, 2004
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N/A
app pub date -
Oct 30, 2000
filing date -
Apr 30, 1998
priority date (Note) -
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Abstract
The present invention provides a RISC processor with a debug interface unit that enables the external replication of the data processing sequence within a RISC processor for debug purposes. The data exchanged between the sequence controller and the instruction decoder are intermediately stored and forwarded via a free bus line to an interface unit. In the interface unit, the data pending at its inputs are forwarded to defined outputs of the interface. This allows the register contents to be co-read in real time. Accordingly, all the required information to perform an efficient error search are displayed for an outside operator who may then monitor the data processing sequence and conduct an error search.
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