Low power apparatus and algorithm for sub-rate bit acquisition and synchronization of high speed clockless data streams
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United States of America Patent
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Jul 20, 2004
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N/A
app pub date -
Feb 9, 2000
filing date -
Feb 9, 2000
priority date (Note) -
Expired
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Abstract
A clockless synchronizer (200) is used for sub-rate bit acquisition and synchronization of high speed clockless data streams. Clockless synchronizer (200) comprises burst detector (210), multi-phase signal generator (220), multi-phase signal router (230), multi-phase signal sampler (240), clock generator (250), correlation control circuit (260), and output data selector (270). Clockless synchronizer (200) is fabricated on a single ASIC, and it is free from the `data rate less than the available clock` limitation.
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