Cache memory capable of reducing area occupied by data memory macro units
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United States of America Patent
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Jul 13, 2004
Grant Date -
Sep 19, 2002
app pub date -
Dec 27, 2001
filing date -
Mar 15, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A cache memory is provided which is capable of reducing areas occupied by data memory macro units and preventing delays in data transmission caused by wirings, thus improving performance of the cache memory. The cache memory is provided with four data memory macro units the number of which is equal to that of ways. Each of the data memory macro units can be accessed simultaneously. A different way number is made associated, for every word address having the same index address, with a data storing position in each of the data memory macro units and data having the same index address and same word address in each of the ways is stored for every data memory.
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