Residue-free solder bumping process

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6759319
APP PUB NO 20020173134A1
SERIAL NO

09858526

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away. The sacrificial layer is etched away to complete the formation of the solder bumps in the manufacture of the integrated circuit device. The etching away of the sacrificial layer insures the complete removal of all of the residue of the aperture mask.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICSSINGAPORE 117685

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Viswanadam, Gautham Singapore, SG 5 31
Wong, Chee Chong Singapore, SG 1 19

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