Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal
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United States of America Patent
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Jun 22, 2004
Grant Date -
Feb 6, 2003
app pub date -
Oct 1, 2002
filing date -
Jun 21, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A test mode control circuit detects designation of a test mode in accordance with a combination of external control signals and address signals, and activates an internal period setting circuit. Internal period setting circuit generates a clock signal having a prescribed period when activated, and applies it to a control circuit. In accordance with the test mode designating signal from test mode setting circuit and the clock signal from internal period setting circuit, control circuit causes an internal address generating circuit to generate an internal address signal successively in synchronization with the clock signal, so that a word line of a memory array is selected.
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