First level cache parity error inject
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United States of America Patent
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Jun 15, 2004
Grant Date -
N/A
app pub date -
Dec 1, 2000
filing date -
Dec 1, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.
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