Scalable multiprocessor system and cache coherence method
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United States of America Patent
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Jun 15, 2004
Grant Date -
Jan 17, 2002
app pub date -
Jun 11, 2001
filing date -
Jun 10, 2000
priority date (Note) -
Expired
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Abstract
The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
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