Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

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United States of America Patent

PATENT NO 6748507
APP PUB NO 20030046514A1
SERIAL NO

10172290

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Abstract

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A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATION1753 SHIMONUMABE NAKAHARA-KU KAWASAKI-SHI KANAGAWA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akao, Yasushi Kokubunji, JP 58 1723
Hasegawa, Atsushi Tachikawa, JP 180 2007
Hayakawa, Akio Hachiouji, JP 17 607
Ito, Yoshitaka Kodaira, JP 96 1278
Kawasaki, Shumpei Tokyo, JP 40 1317
Kurakazu, Keiichi Tokorozawa, JP 40 1027
Matsubara, Kiyoshi Higashimurayama, JP 71 2015
Noguchi, Kouki Tokyo, JP 53 1649
Ohsuga, Hiroshi Hino, JP 16 725

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