Low temperature aluminum planarization process

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United States of America Patent

PATENT NO 6746950
APP PUB NO 20030092255A1
SERIAL NO

09992743

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Abstract

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A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.

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Patent Owner(s)

Patent OwnerAddress
VITESSE SEMICONDUCTOR CORPORATION741 CALLE PLANO CAMARILLO CA 93010

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shan, Ende Colorado Springs, CO 8 92

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