Semiconductor device with stacked memory and logic substrates and method for fabricating the same
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United States of America Patent
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Jun 8, 2004
Grant Date -
Oct 23, 2003
app pub date -
May 22, 2003
filing date -
Jul 31, 2000
priority date (Note) -
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Abstract
Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.
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