Method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor production, and computer program therefor
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United States of America Patent
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Jun 1, 2004
Grant Date -
Mar 6, 2003
app pub date -
Sep 3, 2002
filing date -
Aug 31, 2001
priority date (Note) -
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Abstract
A method of producing a layout for a mask for use in semiconductor production includes a two-stage, iterative optimization of the position of scatter bars in relation to main structures being carried out. In a first stage, following first production of scatter bars and carrying out an OPC, scatter bars are again generated based on the corrected main structures. A renewed OPC is then carried out, followed by the renewed formation of scatter bars. This is repeated until the layout has been optimized sufficiently. Then, in the second stage, defocused exposure of the layout is simulated and, if required, further adaptation of the scatter bars is carried out. The first and second iterative stages can also be employed independently of each other. The common factor in the iterations is that the scatter bar positions are varied with each iteration and is therefore optimized.
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