Semiconductor memory device with mode register and method for controlling deep power down mode therein
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United States of America Patent
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Jun 1, 2004
Grant Date -
Nov 13, 2003
app pub date -
Dec 30, 2002
filing date -
May 13, 2002
priority date (Note) -
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Abstract
Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.
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