Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page
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United States of America Patent
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May 25, 2004
Issued Date -
N/A
app pub date -
Jan 28, 2003
filing date -
Aug 17, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting. An address error exception occurs when the ending address of the vector data to be transferred is not within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined in parallel with determining the starting address of the vector data to be transferred.
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