Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6740964
APP PUB NO 20020060361A1
SERIAL NO

09942962

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Abstract

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A semiconductor package for three-dimensional mounting is provided. The package includes a wiring substrate having a first surface on which a first wiring pattern is formed and a second surface on which a second wiring pattern is formed, the first wiring pattern and second wiring pattern being electrically connected to each other; a semiconductor chip placed on the first surface of the wiring substrate and electrically connected to the first wiring pattern; a sealing resin layer sealing the semiconductor chip and the first wiring pattern; a thickness direction wire passing through the sealing resin layer in a thickness direction and having one end electrically connected to the first wiring pattern and the other end exposed at the surface of the sealing resin layer; and a lower surface connecting electrode formed on the second surface of the wiring substrate and electrically connected to the second wiring pattern.

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Patent Owner(s)

Patent OwnerAddress
LAPIS SEMICONDUCTOR CO LTD2-4-8 SHINYOKOHAMA KOUHOKU-KU YOKOHAMA 222-8575

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sasaki, Takaaki Miyazaki, JP 22 502

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