Fabrication method for circuit board
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United States of America Patent
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May 25, 2004
Grant Date -
Sep 18, 2003
app pub date -
Jun 12, 2002
filing date -
Mar 15, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.
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