Pitch reduction in semiconductor fabrication
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United States of America Patent
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May 11, 2004
Grant Date -
Dec 18, 2003
app pub date -
Jun 12, 2002
filing date -
Jun 12, 2002
priority date (Note) -
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Abstract
A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer. The second polymer layer is used as an etching mask to define the conductive layer. Then, the second polymer layer is removed.
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