Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect
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United States of America Patent
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Apr 6, 2004
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app pub date -
Feb 28, 2002
filing date -
Oct 13, 1995
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Abstract
A number of enhanced logic elements (LEs) are provided to form a reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved IC may further comprises a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for 'level sensitive' as well as 'edge sensitive' circuit design emulations.
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