Ferroelectric memory device using via etch-stop layer and method for manufacturing the same
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United States of America Patent
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Mar 30, 2004
Grant Date -
Sep 11, 2003
app pub date -
Jan 29, 2003
filing date -
Mar 8, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.
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