Array of processors architecture for a space-based network router
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United States of America Patent
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Mar 23, 2004
Grant Date -
N/A
app pub date -
Jul 13, 2000
filing date -
Jul 13, 2000
priority date (Note) -
Expired
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Abstract
A space-based network router architecture (20) is disclosed. The router includes an array-of-processors architecture (20) for routing uplink and downlink traffic of a communications system (10). The architecture comprises multiple node interface chips (26) linked to one another via horizontal and vertical rings (22, 24), thus forming a mesh (21). Associated with each node interface chip (26) is a processor (28) and either a demodulator (30) or modulator (32). Each node interface chip (26) selectively transfers a signal depending upon the particular signal's destination and processing requirements. The router architecture (20) provides scalabitly, fault-tolerance and flexibility, as well as structural advantages over present router systems.
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