Wafer burn-in test and wafer test circuit
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United States of America Patent
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Mar 23, 2004
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N/A
app pub date -
Apr 14, 2003
filing date -
Sep 20, 2001
priority date (Note) -
Expired
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Abstract
A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.
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