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Abstract

A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating 'write fatigue'. The invention provides an integrated circuit, comprising a programmable OR array (24), a programmable AND array (28), coupled to the programmable OR array, and a macrocell output circuit (22). The macrocell uniquely has a ferromagnetic bit (11) and sensor (12) coupled to store remnant output signal, and an output buffer (34), coupled to output the remnant output signal upon receiving an output enable signal. The macrocell may further include a DQ register that contains the ferromagnetic bit. The DQ register may also include a drive coil, which at least partially surrounds the ferromagnetic bit. Drive coils may have a bi-directional current that sets the polarity of the ferromagnetic bit. The bi-directional current may be switched by two sets of transistor pairs (Q10 and Q11). The two sets of transistor pairs may, in turn, be gated by first and second transistor respectively. The first and second transistors may be responsive to a DATA signal that is received when a CLOCK signal is received.

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First Claim