Enhanced chip scale package for wire bond dies
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 23, 2004
Grant Date -
Aug 21, 2003
app pub date -
Feb 19, 2002
filing date -
Nov 2, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane completely surrounds the wire bond signal connections made with the die, enhancing signal integrity. The top ground plane covers the die mounting area, providing grounding and heat spreading for the die. The thermal vias are also positioned in the mounting area, and thermally couple the die to the bottom-side ground plane. The bottom ground plane is positioned within a central area around which the signal connections from the top-side are arranged. Ground pads with attached solder balls are positioned within the bottom ground plane and conduct heat transferred from the die into a primary circuit board on which the carrier is mounted.
First Claim
Other Claims data not available
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 4 Citation Count
- H01L Class
- 1.54 % this patent is cited more than
- 21 Age
