Chip-packaging substrate and test method therefor
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United States of America Patent
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Mar 16, 2004
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app pub date -
Mar 12, 2003
filing date -
Mar 12, 2003
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Abstract
A chip-packaging substrate and test method therefor. The chip-packaging substrate includes at least one package area and a connection area enclosed by and connected to the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.
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