Method of forming an alignment feature in or on a multi-layered semiconductor structure
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United States of America Patent
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Mar 16, 2004
Grant Date -
Jan 10, 2002
app pub date -
May 29, 2001
filing date -
Dec 7, 1999
priority date (Note) -
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Abstract
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
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