Methods for tracing faults in memory components
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United States of America Patent
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Mar 2, 2004
Grant Date -
Oct 31, 2002
app pub date -
Feb 9, 2001
filing date -
Feb 9, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
There are disclosed methods and apparatus for testing memory components for faults, defects or the like, by generating a testing sequence that produces various bit combinations as well as current changes, that when coupled, stresses or fatigues the memory component, and allows for the evaluation of single bits. The testing sequence is provided in cycles, formed of complement word pairs of N bit words. The first, or initial, cycle typically includes a first word of all binary zeros. Successive or subsequent cycles include a shifted bit in each subsequent first word. The testing pattern is written into the memory component(s) under test and corresponding words are read from the memory component(s). The written and read words are then compared, with this comparison analyzed for detection of faults, defects or the like in the memory component(s).
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